The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device including a landing plug functioning as a contact plug.
As the integration scale of a semiconductor device has been increased, a sufficient process margin needs to be secured during a bit line or storage node contact process of a capacitor. Accordingly, a landing plug which is a kind of a contact plug is formed by performing a chemical mechanical polishing (CMP) process.
FIGS. 1A to 1D are cross-sectional views illustrating a typical method for fabricating a semiconductor device including a landing plug.
As shown in FIG. 1A, a plurality of gate lines 15 are formed over a substrate 10. Each gate line 15 is formed in a stack structure including a gate oxide layer 11, a polysilicon layer 12, a tungsten silicide layer 13, and a nitride-based layer 14 for use as a hard mask. An oxide layer 16 and a nitride layer 17 are sequentially formed over the substrate structure including the gate lines 15. The nitride layer 17 functions as an etch barrier layer for self-aligned contact (SAC) when forming a contact hole wherein a landing plug is to be formed. Then, an inter-layer insulation layer 18 is formed over the substrate structure.
Referring to FIG. 1B, a portion of the inter-layer insulation layer 18 is etched using the nitride layer 17 formed between the gate lines 15 as an etch barrier layer. The remaining inter-layer insulation layer 18 is denoted with reference numeral 18A. Thus, a contact hole 19 exposing a portion of the nitride layer 17 is formed. Referring to FIG. 1C, a buffer oxide layer 20 is formed over the substrate structure and in the contact hole 19 to compensate an insufficient lateral thickness of the nitride-based layers 14.
Referring to FIG. 1D, a cleaning process is performed to remove a given portion of the buffer oxide layer 20 existing over the substrate 10 between the gate lines 15. The remaining buffer oxide layer 20 is denoted with reference numeral 20A. Afterwards, an etch-back process is performed to etch the nitride layer 17 and the oxide layer 16 exposed in the contact hole 19. The remaining nitride layer 17 and the remaining oxide layer 16 after performing the etch-back process are denoted with reference numerals 17A and 16A, respectively. As a result, an opening ‘O’ exposing the substrate 10 between the gate lines 15 is formed.
However, the aforementioned etch-back process is performed with etch selectivity of approximately 1:1 between the oxide layers, i.e., the oxide layer 16 and the buffer oxide layer 20, and the nitride layers, i.e., the nitride layer 17 and the nitride-based layers 14. Accordingly, loss ‘L’ may be produced over the nitride-based layers 14 for use as a hard mask simultaneous to the formation of the opening ‘O’ exposing the substrate 10, thereby generating short-circuit or leakage current. Thus, device characteristics may deteriorate. The further etched remaining inter-layer insulation layer 18A is denoted with reference numeral 18B.
A thickness of the nitride-based layers 14 for use as a hard mask itself needs to be increased to remove the loss ‘L’. However, if the thickness of the nitride-based layers 14 increases, an aspect ratio also increases. Thus, a gap-filling margin may be insufficient while forming the inter-layer insulation layer after the formation of the gate lines 15. As a result, a void may be produced in the inter-layer insulation layer between the gate lines 15.